-- G. Gora
-- MSWSiS 2020


library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity CntMod12 is
	port(
		clk : in std_logic;
		reset_n : in std_logic := '1';
		enable : in std_logic := '1';
		
		q3, q2, q1, q0 : out std_logic
	);
end entity;


architecture CntMod12 of CntMod12 is

	signal cnt : unsigned(3 downto 0) := (others => '0');

begin

	process(clk, reset_n)
	begin
		if(reset_n = '0')then
			cnt <= (others => '0');
		elsif rising_edge(clk) then
			if(enable = '1')then
				if(cnt < 11)then
					cnt <= cnt + "0001";
				else
					cnt <= (others => '0');		
				end if;
			end if;
		end if;		
	end process;

	q3 <= cnt(3);
	q2 <= cnt(2);
	q1 <= cnt(1);
	q0 <= cnt(0);

end architecture;