| Hierarchy |
Input |
Constant Input |
Unused Input |
Floating Input |
Output |
Constant Output |
Unused Output |
Floating Output |
Bidir |
Constant Bidir |
Unused Bidir |
Input only Bidir |
Output only Bidir |
| inst9 |
2 |
2 |
0 |
2 |
3 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| inst |
2 |
2 |
0 |
2 |
3 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| inst11|rst_controller_001|alt_rst_req_sync_uq1 |
2 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst11|rst_controller_001|alt_rst_sync_uq1 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst11|rst_controller_001 |
33 |
30 |
0 |
30 |
2 |
30 |
30 |
30 |
0 |
0 |
0 |
0 |
0 |
| inst11|rst_controller|alt_rst_req_sync_uq1 |
2 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst11|rst_controller|alt_rst_sync_uq1 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst11|rst_controller |
33 |
31 |
0 |
31 |
2 |
31 |
31 |
31 |
0 |
0 |
0 |
0 |
0 |
| inst11|irq_mapper |
4 |
30 |
2 |
30 |
32 |
30 |
30 |
30 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|avalon_st_adapter_009|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|avalon_st_adapter_009 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|avalon_st_adapter_008|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|avalon_st_adapter_008 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|avalon_st_adapter_007|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|avalon_st_adapter_007 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|avalon_st_adapter_006|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|avalon_st_adapter_006 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|avalon_st_adapter_005|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|avalon_st_adapter_005 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|avalon_st_adapter_004|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|avalon_st_adapter_004 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|avalon_st_adapter_003|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|avalon_st_adapter_003 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|avalon_st_adapter_002|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|avalon_st_adapter_002 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|avalon_st_adapter_001|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|avalon_st_adapter_001 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|avalon_st_adapter|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|avalon_st_adapter |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|rsp_mux_001|arb|adder |
40 |
20 |
0 |
20 |
20 |
20 |
20 |
20 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|rsp_mux_001|arb |
14 |
0 |
4 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|rsp_mux_001 |
1093 |
0 |
0 |
0 |
119 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|rsp_mux|arb|adder |
40 |
20 |
0 |
20 |
20 |
20 |
20 |
20 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|rsp_mux|arb |
14 |
0 |
4 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|rsp_mux |
1093 |
0 |
0 |
0 |
119 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|rsp_demux_009 |
113 |
4 |
2 |
4 |
219 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|rsp_demux_008 |
113 |
4 |
2 |
4 |
219 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|rsp_demux_007 |
113 |
4 |
2 |
4 |
219 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|rsp_demux_006 |
113 |
4 |
2 |
4 |
219 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|rsp_demux_005 |
113 |
4 |
2 |
4 |
219 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|rsp_demux_004 |
113 |
4 |
2 |
4 |
219 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|rsp_demux_003 |
113 |
4 |
2 |
4 |
219 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|rsp_demux_002 |
113 |
4 |
2 |
4 |
219 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|rsp_demux_001 |
113 |
4 |
2 |
4 |
219 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|rsp_demux |
113 |
4 |
2 |
4 |
219 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|cmd_mux_009|arb|adder |
8 |
2 |
0 |
2 |
4 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|cmd_mux_009|arb |
6 |
0 |
1 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|cmd_mux_009 |
221 |
0 |
0 |
0 |
111 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|cmd_mux_008|arb|adder |
8 |
2 |
0 |
2 |
4 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|cmd_mux_008|arb |
6 |
0 |
1 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|cmd_mux_008 |
221 |
0 |
0 |
0 |
111 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|cmd_mux_007|arb|adder |
8 |
2 |
0 |
2 |
4 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|cmd_mux_007|arb |
6 |
0 |
1 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|cmd_mux_007 |
221 |
0 |
0 |
0 |
111 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|cmd_mux_006|arb|adder |
8 |
2 |
0 |
2 |
4 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|cmd_mux_006|arb |
6 |
0 |
1 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|cmd_mux_006 |
221 |
0 |
0 |
0 |
111 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|cmd_mux_005|arb|adder |
8 |
2 |
0 |
2 |
4 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|cmd_mux_005|arb |
6 |
0 |
1 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|cmd_mux_005 |
221 |
0 |
0 |
0 |
111 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|cmd_mux_004|arb|adder |
8 |
2 |
0 |
2 |
4 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|cmd_mux_004|arb |
6 |
0 |
1 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|cmd_mux_004 |
221 |
0 |
0 |
0 |
111 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|cmd_mux_003|arb|adder |
8 |
2 |
0 |
2 |
4 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|cmd_mux_003|arb |
6 |
0 |
1 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|cmd_mux_003 |
221 |
0 |
0 |
0 |
111 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|cmd_mux_002|arb|adder |
8 |
2 |
0 |
2 |
4 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|cmd_mux_002|arb |
6 |
0 |
1 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|cmd_mux_002 |
221 |
0 |
0 |
0 |
111 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|cmd_mux_001|arb|adder |
8 |
2 |
0 |
2 |
4 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|cmd_mux_001|arb |
6 |
0 |
1 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|cmd_mux_001 |
221 |
0 |
0 |
0 |
111 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|cmd_mux|arb|adder |
8 |
2 |
0 |
2 |
4 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|cmd_mux|arb |
6 |
0 |
1 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|cmd_mux |
221 |
0 |
0 |
0 |
111 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|cmd_demux_001 |
121 |
100 |
2 |
100 |
1091 |
100 |
100 |
100 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|cmd_demux |
121 |
100 |
2 |
100 |
1091 |
100 |
100 |
100 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|router_011|the_default_decode |
0 |
10 |
0 |
10 |
10 |
10 |
10 |
10 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|router_011 |
102 |
0 |
2 |
0 |
110 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|router_010|the_default_decode |
0 |
10 |
0 |
10 |
10 |
10 |
10 |
10 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|router_010 |
102 |
0 |
2 |
0 |
110 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|router_009|the_default_decode |
0 |
10 |
0 |
10 |
10 |
10 |
10 |
10 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|router_009 |
102 |
0 |
2 |
0 |
110 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|router_008|the_default_decode |
0 |
10 |
0 |
10 |
10 |
10 |
10 |
10 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|router_008 |
102 |
0 |
2 |
0 |
110 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|router_007|the_default_decode |
0 |
10 |
0 |
10 |
10 |
10 |
10 |
10 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|router_007 |
102 |
0 |
2 |
0 |
110 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|router_006|the_default_decode |
0 |
10 |
0 |
10 |
10 |
10 |
10 |
10 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|router_006 |
102 |
0 |
2 |
0 |
110 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|router_005|the_default_decode |
0 |
10 |
0 |
10 |
10 |
10 |
10 |
10 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|router_005 |
102 |
0 |
2 |
0 |
110 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|router_004|the_default_decode |
0 |
10 |
0 |
10 |
10 |
10 |
10 |
10 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|router_004 |
102 |
0 |
2 |
0 |
110 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|router_003|the_default_decode |
0 |
10 |
0 |
10 |
10 |
10 |
10 |
10 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|router_003 |
102 |
0 |
2 |
0 |
110 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|router_002|the_default_decode |
0 |
10 |
0 |
10 |
10 |
10 |
10 |
10 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|router_002 |
102 |
0 |
2 |
0 |
110 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|router_001|the_default_decode |
0 |
14 |
0 |
14 |
14 |
14 |
14 |
14 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|router_001 |
102 |
0 |
6 |
0 |
110 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|router|the_default_decode |
0 |
14 |
0 |
14 |
14 |
14 |
14 |
14 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|router |
102 |
0 |
6 |
0 |
110 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|hex4to5_s1_agent_rsp_fifo |
142 |
39 |
0 |
39 |
101 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|hex4to5_s1_agent|uncompressor |
34 |
1 |
0 |
1 |
32 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|hex4to5_s1_agent |
287 |
39 |
47 |
39 |
298 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|hex0to3_s1_agent_rsp_fifo |
142 |
39 |
0 |
39 |
101 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|hex0to3_s1_agent|uncompressor |
34 |
1 |
0 |
1 |
32 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|hex0to3_s1_agent |
287 |
39 |
47 |
39 |
298 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|key_s1_agent_rsp_fifo |
142 |
39 |
0 |
39 |
101 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|key_s1_agent|uncompressor |
34 |
1 |
0 |
1 |
32 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|key_s1_agent |
287 |
39 |
47 |
39 |
298 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|b_sig_in_s1_agent_rsp_fifo |
142 |
39 |
0 |
39 |
101 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|b_sig_in_s1_agent|uncompressor |
34 |
1 |
0 |
1 |
32 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|b_sig_in_s1_agent |
287 |
39 |
47 |
39 |
298 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|a_sig_in_s1_agent_rsp_fifo |
142 |
39 |
0 |
39 |
101 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|a_sig_in_s1_agent|uncompressor |
34 |
1 |
0 |
1 |
32 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|a_sig_in_s1_agent |
287 |
39 |
47 |
39 |
298 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|leds_s1_agent_rsp_fifo |
142 |
39 |
0 |
39 |
101 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|leds_s1_agent|uncompressor |
34 |
1 |
0 |
1 |
32 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|leds_s1_agent |
287 |
39 |
47 |
39 |
298 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|onchip_memory2_0_s1_agent_rsp_fifo |
142 |
39 |
0 |
39 |
101 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|onchip_memory2_0_s1_agent|uncompressor |
34 |
1 |
0 |
1 |
32 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|onchip_memory2_0_s1_agent |
287 |
39 |
47 |
39 |
298 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|nios2_gen2_0_debug_mem_slave_agent_rsp_fifo |
142 |
39 |
0 |
39 |
101 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|nios2_gen2_0_debug_mem_slave_agent|uncompressor |
34 |
1 |
0 |
1 |
32 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|nios2_gen2_0_debug_mem_slave_agent |
287 |
39 |
47 |
39 |
298 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|sysid_control_slave_agent_rsp_fifo |
142 |
39 |
0 |
39 |
101 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|sysid_control_slave_agent|uncompressor |
34 |
1 |
0 |
1 |
32 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|sysid_control_slave_agent |
287 |
39 |
47 |
39 |
298 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|jtag_uart_avalon_jtag_slave_agent_rsp_fifo |
142 |
39 |
0 |
39 |
101 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|jtag_uart_avalon_jtag_slave_agent|uncompressor |
34 |
1 |
0 |
1 |
32 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|jtag_uart_avalon_jtag_slave_agent |
287 |
39 |
47 |
39 |
298 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|nios2_gen2_0_instruction_master_agent |
173 |
39 |
78 |
39 |
134 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|nios2_gen2_0_data_master_agent |
173 |
39 |
78 |
39 |
134 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|hex4to5_s1_translator |
101 |
6 |
19 |
6 |
70 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|hex0to3_s1_translator |
101 |
6 |
19 |
6 |
70 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|key_s1_translator |
101 |
6 |
19 |
6 |
36 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|b_sig_in_s1_translator |
101 |
6 |
19 |
6 |
36 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|a_sig_in_s1_translator |
101 |
6 |
19 |
6 |
70 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|leds_s1_translator |
101 |
6 |
19 |
6 |
70 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|onchip_memory2_0_s1_translator |
101 |
7 |
4 |
7 |
87 |
7 |
7 |
7 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|nios2_gen2_0_debug_mem_slave_translator |
101 |
5 |
9 |
5 |
82 |
5 |
5 |
5 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|sysid_control_slave_translator |
101 |
6 |
17 |
6 |
35 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|jtag_uart_avalon_jtag_slave_translator |
101 |
5 |
20 |
5 |
70 |
5 |
5 |
5 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|nios2_gen2_0_instruction_master_translator |
102 |
51 |
0 |
51 |
94 |
51 |
51 |
51 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0|nios2_gen2_0_data_master_translator |
102 |
12 |
0 |
12 |
94 |
12 |
12 |
12 |
0 |
0 |
0 |
0 |
0 |
| inst11|mm_interconnect_0 |
401 |
0 |
0 |
0 |
352 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst11|sysid |
3 |
15 |
2 |
15 |
32 |
15 |
15 |
15 |
0 |
0 |
0 |
0 |
0 |
| inst11|onchip_memory2_0|the_altsyncram|auto_generated|mux2 |
65 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst11|onchip_memory2_0|the_altsyncram|auto_generated|decode3 |
2 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst11|onchip_memory2_0|the_altsyncram|auto_generated |
53 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst11|onchip_memory2_0 |
57 |
1 |
1 |
1 |
32 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst11|nios2_gen2_0|cpu|the_unsaved_nios2_gen2_0_cpu_nios2_oci|the_unsaved_nios2_gen2_0_cpu_debug_slave_wrapper|the_unsaved_nios2_gen2_0_cpu_debug_slave_sysclk |
43 |
0 |
0 |
0 |
48 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst11|nios2_gen2_0|cpu|the_unsaved_nios2_gen2_0_cpu_nios2_oci|the_unsaved_nios2_gen2_0_cpu_debug_slave_wrapper|the_unsaved_nios2_gen2_0_cpu_debug_slave_tck |
130 |
0 |
1 |
0 |
43 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst11|nios2_gen2_0|cpu|the_unsaved_nios2_gen2_0_cpu_nios2_oci|the_unsaved_nios2_gen2_0_cpu_debug_slave_wrapper |
123 |
0 |
0 |
0 |
50 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst11|nios2_gen2_0|cpu|the_unsaved_nios2_gen2_0_cpu_nios2_oci|the_unsaved_nios2_gen2_0_cpu_nios2_ocimem|unsaved_nios2_gen2_0_cpu_ociram_sp_ram|the_altsyncram|auto_generated |
47 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst11|nios2_gen2_0|cpu|the_unsaved_nios2_gen2_0_cpu_nios2_oci|the_unsaved_nios2_gen2_0_cpu_nios2_ocimem|unsaved_nios2_gen2_0_cpu_ociram_sp_ram |
47 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst11|nios2_gen2_0|cpu|the_unsaved_nios2_gen2_0_cpu_nios2_oci|the_unsaved_nios2_gen2_0_cpu_nios2_ocimem |
92 |
0 |
6 |
0 |
65 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst11|nios2_gen2_0|cpu|the_unsaved_nios2_gen2_0_cpu_nios2_oci|the_unsaved_nios2_gen2_0_cpu_nios2_avalon_reg |
48 |
0 |
29 |
0 |
68 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst11|nios2_gen2_0|cpu|the_unsaved_nios2_gen2_0_cpu_nios2_oci|the_unsaved_nios2_gen2_0_cpu_nios2_oci_im |
54 |
38 |
51 |
38 |
47 |
38 |
38 |
38 |
0 |
0 |
0 |
0 |
0 |
| inst11|nios2_gen2_0|cpu|the_unsaved_nios2_gen2_0_cpu_nios2_oci|the_unsaved_nios2_gen2_0_cpu_nios2_oci_pib |
0 |
36 |
0 |
36 |
36 |
36 |
36 |
36 |
0 |
0 |
0 |
0 |
0 |
| inst11|nios2_gen2_0|cpu|the_unsaved_nios2_gen2_0_cpu_nios2_oci|the_unsaved_nios2_gen2_0_cpu_nios2_oci_fifo|the_unsaved_nios2_gen2_0_cpu_nios2_oci_fifo_cnt_inc |
5 |
0 |
0 |
0 |
5 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst11|nios2_gen2_0|cpu|the_unsaved_nios2_gen2_0_cpu_nios2_oci|the_unsaved_nios2_gen2_0_cpu_nios2_oci_fifo|the_unsaved_nios2_gen2_0_cpu_nios2_oci_fifo_wrptr_inc |
4 |
2 |
0 |
2 |
4 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| inst11|nios2_gen2_0|cpu|the_unsaved_nios2_gen2_0_cpu_nios2_oci|the_unsaved_nios2_gen2_0_cpu_nios2_oci_fifo|the_unsaved_nios2_gen2_0_cpu_nios2_oci_compute_input_tm_cnt |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst11|nios2_gen2_0|cpu|the_unsaved_nios2_gen2_0_cpu_nios2_oci|the_unsaved_nios2_gen2_0_cpu_nios2_oci_fifo |
115 |
0 |
65 |
0 |
36 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst11|nios2_gen2_0|cpu|the_unsaved_nios2_gen2_0_cpu_nios2_oci|the_unsaved_nios2_gen2_0_cpu_nios2_oci_dtrace|unsaved_nios2_gen2_0_cpu_nios2_oci_trc_ctrl_td_mode |
9 |
0 |
6 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst11|nios2_gen2_0|cpu|the_unsaved_nios2_gen2_0_cpu_nios2_oci|the_unsaved_nios2_gen2_0_cpu_nios2_oci_dtrace |
103 |
0 |
92 |
0 |
72 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst11|nios2_gen2_0|cpu|the_unsaved_nios2_gen2_0_cpu_nios2_oci|the_unsaved_nios2_gen2_0_cpu_nios2_oci_itrace |
24 |
53 |
24 |
53 |
53 |
53 |
53 |
53 |
0 |
0 |
0 |
0 |
0 |
| inst11|nios2_gen2_0|cpu|the_unsaved_nios2_gen2_0_cpu_nios2_oci|the_unsaved_nios2_gen2_0_cpu_nios2_oci_dbrk |
88 |
0 |
0 |
0 |
92 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst11|nios2_gen2_0|cpu|the_unsaved_nios2_gen2_0_cpu_nios2_oci|the_unsaved_nios2_gen2_0_cpu_nios2_oci_xbrk |
54 |
5 |
51 |
5 |
6 |
5 |
5 |
5 |
0 |
0 |
0 |
0 |
0 |
| inst11|nios2_gen2_0|cpu|the_unsaved_nios2_gen2_0_cpu_nios2_oci|the_unsaved_nios2_gen2_0_cpu_nios2_oci_break |
51 |
36 |
6 |
36 |
71 |
36 |
36 |
36 |
0 |
0 |
0 |
0 |
0 |
| inst11|nios2_gen2_0|cpu|the_unsaved_nios2_gen2_0_cpu_nios2_oci|the_unsaved_nios2_gen2_0_cpu_nios2_oci_debug |
50 |
1 |
30 |
1 |
7 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst11|nios2_gen2_0|cpu|the_unsaved_nios2_gen2_0_cpu_nios2_oci |
156 |
0 |
0 |
0 |
69 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst11|nios2_gen2_0|cpu|unsaved_nios2_gen2_0_cpu_register_bank_b|the_altsyncram|auto_generated |
44 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst11|nios2_gen2_0|cpu|unsaved_nios2_gen2_0_cpu_register_bank_b |
44 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst11|nios2_gen2_0|cpu|unsaved_nios2_gen2_0_cpu_register_bank_a|the_altsyncram|auto_generated |
44 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst11|nios2_gen2_0|cpu|unsaved_nios2_gen2_0_cpu_register_bank_a |
44 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst11|nios2_gen2_0|cpu|the_unsaved_nios2_gen2_0_cpu_test_bench |
288 |
3 |
254 |
3 |
33 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
| inst11|nios2_gen2_0|cpu |
149 |
1 |
30 |
1 |
111 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst11|nios2_gen2_0 |
149 |
0 |
0 |
0 |
110 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst11|jtag_uart|the_unsaved_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|wr_ptr |
4 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst11|jtag_uart|the_unsaved_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|rd_ptr_count |
4 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst11|jtag_uart|the_unsaved_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|FIFOram |
24 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst11|jtag_uart|the_unsaved_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|fifo_state|count_usedw |
5 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst11|jtag_uart|the_unsaved_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|fifo_state |
5 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst11|jtag_uart|the_unsaved_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo |
13 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst11|jtag_uart|the_unsaved_jtag_uart_scfifo_r|rfifo|auto_generated |
12 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst11|jtag_uart|the_unsaved_jtag_uart_scfifo_r |
13 |
0 |
1 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst11|jtag_uart|the_unsaved_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|wr_ptr |
4 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst11|jtag_uart|the_unsaved_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|rd_ptr_count |
4 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst11|jtag_uart|the_unsaved_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|FIFOram |
24 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst11|jtag_uart|the_unsaved_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|fifo_state|count_usedw |
5 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst11|jtag_uart|the_unsaved_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|fifo_state |
5 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst11|jtag_uart|the_unsaved_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo |
13 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst11|jtag_uart|the_unsaved_jtag_uart_scfifo_w|wfifo|auto_generated |
12 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst11|jtag_uart|the_unsaved_jtag_uart_scfifo_w |
12 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst11|jtag_uart |
38 |
10 |
23 |
10 |
34 |
10 |
10 |
10 |
0 |
0 |
0 |
0 |
0 |
| inst11|hex4to5 |
38 |
16 |
16 |
16 |
48 |
16 |
16 |
16 |
0 |
0 |
0 |
0 |
0 |
| inst11|hex0to3 |
38 |
0 |
0 |
0 |
64 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst11|leds |
38 |
24 |
24 |
24 |
40 |
24 |
24 |
24 |
0 |
0 |
0 |
0 |
0 |
| inst11|key |
6 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst11|b_sig_in |
5 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst11|a_sig_in |
39 |
0 |
31 |
0 |
33 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst11 |
6 |
1 |
0 |
1 |
56 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |